Developing PL Kernels with Vitis HLS - 2024.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2024-05-30
Version
2024.1 English

PL kernels can be developed using C/C++ code and the Vitis HLS tool. The Vitis HLS tool simplifies the use of C/C++ functions for implementation as PL kernels in the Vitis application acceleration development flow.

The Vitis HLS tool automates much of the code modifications required to implement and optimize the C/C++ code in programmable logic and to achieve low latency and high throughput. The Vitis HLS tool allows inference of required pragmas to produce the right interface for your function arguments and to pipeline loops and functions within your code.

The Vitis HLS design flow includes the following main steps:

  1. Compile, simulate, and debug the C/C++ algorithm.
  2. View reports to analyze and optimize the design.
  3. Synthesize the C algorithm into an RTL design.
  4. Verify the RTL implementation using the Vitis HLS co-simulation flow.
  5. Compile the RTL implementation into a compiled object file (.xo extension), or export to an RTL IP.

For more information, see the Create PL Kernels Using HLS section of the Versal Adaptive SoC Design Process Documentation: Hardware, IP, and Platform Development Guided - Platform.