VCU Encoder/Decoder Features - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

The VCU encoder/decoder supports the following major features:

Region of Interest Encoding: Region of Interest Encoding tags regions in a video frame to be encoded with user supplied quality (high, medium, low, and don’t-care) relative to the picture background (untagged region).

Scene Change Detection: SCD IP generates the SCD event which is passed along with the buffer to the encoder, where the encoder makes decisions to insert an I-frame instead of a P-frame or a B-frame. Inserting an I-frame at the place where a scene is changed would retain the quality of the video.

Interlaced Video: VCU supports encoding and decoding of H265 interlaced video.

DCI-4k Encode/Decode: VCU is capable of encoding or decoding at 4096x2160p60, provided the VCU Core-clk frequency is set to 712 MHz.

Low-Latency (LLP1): The frame is divided into multiple slices; the VCU encoder output and decoder input are processed in slice mode. The VCU Encoder input and Decoder output still works in frame mode.

Low-Latency (LLP2): The frame is divided into multiple slices; the VCU encoder output and decoder input are processed in slice mode. The producer (Capture DMA) and the consumer (VCU Encoder) works on the same buffer by having synchronization IP in place. There is no sync IP in between decoder and display. The decoder will signal the display component when half of input frame is ready.

XAVC: The VCU encoder can produce xAVC Intra or xAVC Long GOP compliant bitstreams. XAVC is mainly used for video record use-cases, as h264parse does not support XAVC parsing. Serial and streaming use-cases might not be valid as the parser does not support these.

Note: For more information on VCU Encoder and Decoder features, Refer to the H.264/H.265 Video Codec Unit LogiCORE IP Product Guide (PG252) [Ref 21] .