SDI TX Display Pipeline - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2023.1 English

The SDI TX display pipeline is shown in This Figure .

Figure 5-9: SDI TX Display Pipeline

X-Ref Target - Figure 5-9


The SMPTE UHD-SDI Transmitter Subsystem accepts AXI4 Video streams and outputs native SDI streams by using AMD transceivers as the physical layer.

The Video Mixer enables you to mix video layers and allows mixing up to four streaming or memory layers. Each layer can be up to 4K resolution and can perform color space conversion. The TRD design uses memory layer 1 to fetch video data.