HDMI RX Capture Pipeline - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2023.1 English

The HDMI receiver capture pipeline is shown in This Figure .

Figure 5-4: HDMI Video Capture Pipeline

X-Ref Target - Figure 5-4


This pipeline consists of four main components, each of them controlled by the APU via an AXI4-Lite base register interface:

The Video PHY Controller (VPHY) enables plug-and-play connectivity with Video Transmit or Receive Subsystems. The interface between the media access control (MAC) and physical (PHY) layers are standardized to enable ease of use in accessing shared gigabit-transceiver (GT) resources. The data recovery unit (DRU) is used to support lower line rates for the HDMI protocol. An AXI4-Lite register interface is provided to enable dynamic accesses of transceiver controls/status. For more information refer to the Video PHY Controller LogiCORE IP Product Guide (PG230) [Ref 11] .

The HDMI Receiver Subsystem (HDMI RX) interfaces with PHY layers and provides HDMI decoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI RX-related IP subcores and outputs them as a single IP. The subsystem receives the captured TMDS data from the video PHY layer. It then extracts the video stream from the HDMI stream and in this design converts it to an AXI4-Stream output interface. For more information, see the HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236) [Ref 12] .

The Video Processing Subsystem (VPSS) is a collection of video processing IP subcores. In this design, the VPSS uses the Video Scaler only configuration which provides scaling, color space conversion, and chroma resampling functionality. The VPSS takes AXI4-Stream input data from the HDMI RX Subsystem and depending on the input format and resolution, converts and scales it to the desired output format and resolution again using AXI4-Stream. A GPIO is used to reset the subsystem between resolution changes. For more information, see the Video Processing Subsystem Product Guide (PG231) [Ref 13] .

The Video Frame Buffer Write IP uses the same configuration as the one in the TPG capture pipeline. It takes AXI4-Stream input data from the VPSS and converts it to memory-mapped AXI4 format. The output is connected to the HP1 high performance PS/PL interface via an AXI interconnect. For each video frame transfer, an interrupt is generated. A GPIO is used to reset the IP between resolution changes. To support YUV444 in the HDMI capture, this format is enabled in the Frame Buffer Write IP.

Similar to the TPG pipeline, the HDMI RX, VPSS Video Scaler, and Frame Buffer Write IPs are configured to transport two pixels per clock (ppc), enabling up to 2160p60 performance. In the DCI4K pipeline, the resolution is 4096 x 2160.