Low Latency Pipeline - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2023.1 English

The low latency pipeline is shown in This Figure .

Figure 5-13: Low Latency Pipeline

X-Ref Target - Figure 5-13


It is possible to reduce VCU processing latency from one frame to one-frame/num-slices. The Sync IP element is responsible for synchronizing buffers between the Capture DMA and the VCU encoder, and the VCU Decoder and Display element. The Sync IP does AXI transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of granularity at the Video Buffer level. The Low Latency Pipeline has these features:

Sync IP can track up to four producer transactions simultaneously (four channels)

Each channel can track up to three buffer sets

Each buffer set has a luma buffer and chroma buffer

Each consumer port can hold 256 AXI transactions, without back-pressure to the consumer

Encoder mode Sync IP supports four simultaneous channels for tracking and control

Decoder mode Sync IP supports two simultaneous channels for tracking and control