Boot Process - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Document ID
Release Date
2023.1 English

The reference design uses a non-secure boot flow and SD boot mode. The sequence diagram in This Figure shows the exact steps and order in which the individual boot components are loaded and executed.

Figure 4-1: Boot Flow Sequence

X-Ref Target - Figure 4-1


The platform management unit (PMU) is responsible for handling primary pre-boot tasks and is the first unit to wake up after power-on reset (POR). After the initial boot process, the PMU continues to run and is responsible for handling various clocks and resets of the system as well as system power management. In the pre-configuration stage, the PMU executes the PMU ROM and releases the reset of the configuration security unit (CSU). It then enters the PMU server mode where it monitors power.

The CSU handles the configuration stages and executes the boot ROM as soon as it comes out of reset. The boot ROM determines the boot mode by reading the boot mode register, it initializes the on-chip memory (OCM), and reads the boot header. The CSU loads the PMU firmware into the PMU RAM and signals to the PMU to execute the firmware, which provides advanced management features instead of the PMU ROM. It then loads the first stage boot loader (FSBL) into OCM and switches into tamper monitoring mode.

In this design, the FSBL is executed on APU-0. It initializes the PS and configures the PL and APU based on the boot image header information. The following steps are performed:

1. The PL is configured with a bitstream and the PL reset is deasserted.

2. The Arm trusted firmware (ATF) is loaded into OCM and executed on APU-0.

3. The second stage boot loader U-Boot is loaded into DDR to be executed by APU-0.

Note: At this point, RPU-1 is still held in reset because no executable has been loaded thus far.

For more information on the boot process, see chapters Programming View of Zynq UltraScale+ MPSoC Devices and System Boot and Configuration in Zynq UltraScale+ MPSoC Software Developer Guide (UG1137) [Ref 7] , and chapter Boot and Configuration in Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 8] .