Introduction - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)
Document ID
UG1250
Release Date
2023-05-16
Version
2023.1 English

This chapter describes the targeted reference design (TRD) hardware architecture. This Figure shows a block diagram of the design components inside the PS and PL on the ZCU106 base board and the LI-IMX274MIPI-FMC image sensor daughter card.

Figure 5-1: Hardware Block Diagram

X-Ref Target - Figure 5-1

X19300-hw-block-diag.jpg

At a high level, the design consists of these three types of video pipelines:

• Capture/Input Pipelines

• Processing Pipelines

• Display/Output Pipelines