The Zynq device is a heterogeneous, multi-processing SoC built on the 16-nm FinFET technology. This Figure shows a high-level block diagram of the device architecture and key building blocks inside the processing system (PS) and the programmable logic (PL).
The MPSoC key features include:
• Application processing unit (APU) with a 64-bit quad-core Arm® Cortex™-A53 processor
• Real-time processing unit (RPU) with a 32-bit dual-core Arm Cortex-R5 processor
• Multimedia blocks
° Graphics processing unit (GPU) Arm Mali-400MP2
° Video codec (encoder/decoder) unit up to 4K (3840 x 2160) 60 frames per second (FPS)
° DisplayPort controller interface up to 4K (3840 x 2160) 30 FPS
• High-speed peripherals
° PCIe root complex and Endpoint (Gen1 or Gen2 x1, x2, and x4 lanes)
° USB 3.0/2.0 with host, device and on-the-go (OTG) modes
° SATA 3.1 host
• Low-speed peripherals
° Gigabit Ethernet, controller area network (CAN), universal asynchronous receiver-transmitter (UART), Serial Peripheral Interface (SPI), Quad SPI, NAND flash memory, Secure Digital embedded Multimedia Card (SD/eMMC), inter IC (I2C), and general purpose I/O (GPIO)
• Platform management unit (PMU)
• Configuration security unit (CSU)
• 6-port DDR controller with error correction code (ECC), supporting x32 and x64 DDR4/3/3L and LPDDR4/3