TPG Capture Pipeline - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2023.1 English

The TPG capture pipeline is shown in This Figure .

Figure 5-3: TPG Video Capture Pipeline

X-Ref Target - Figure 5-3


This pipeline consists of three main components, each of them controlled by the APU via an AXI4-Lite based register interface:

The Video Timing Controller (VTC) generates video timing signals including horizontal and vertical sync and blanking signals. The timing signals are converted to AXI4-Stream using the video-to-AXI4-Stream bridge with the data bus tied off. The video timing over AXI4-Stream bus is connected to the input interface of the TPG, thus making the TPG behave like a timing-accurate video source with a set frame rate as opposed to using the free-running mode.

The Video Test Pattern Generator (TPG) can be configured to generate various test patterns including color bars, zone plates, moving ramps, moving boxes and more. The color space format is configurable and set to YUV 4:2:0 in this design. For more information, see the Video Test Pattern Generator LogiCORE IP Product Guide (PG103) [Ref 9] .

The Video Frame Buffer Write IP provides high-bandwidth direct memory access between memory and AXI4-Stream video type target peripherals, which support the AXI4-Stream Video protocol. In this pipeline, the IP takes AXI4-Stream input data from the TPG and converts it to memory-mapped AXI4 format. The output is connected to the HP1 high performance PS/PL interface via an AXI interconnect. For each video frame transfer, an interrupt is generated. A GPIO is used to reset the core between resolution changes. For more information refer to the Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278) [Ref 10] .