SDI RX Capture Pipeline - 2023.1 English

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

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2023.1 English

The SDI RX capture pipeline is shown in This Figure .

Figure 5-6: SDI RX Capture Pipeline

X-Ref Target - Figure 5-6


The serial digital interface (SDI) Receiver Subsystem implements an SDI receive interface in accordance with the SDI family of standards. The subsystem receives video from a native SDI interface and generates AXI4-Stream video. The SMPTE UHD-SDI receiver core receives multiplexed native SDI data streams and generates non-multiplexed 10-bit SDI data streams in YUV422 format.

The Video Frame Buffer Write IP is used as the Frame Grabber logic, which is designed to allow efficient and high bandwidth access between AXI4-Streaming Video In interfaces to the AMD Zynq™ UltraScale+™ MPSoC PS DDR memory. The Video Frame Buffer IP can write a variety of video formats to the Zynq UltraScale+ MPSoC PS DDR memory.