The core has two reset signals:
- s_axi_reg_aresetn
- An active-Low reset for the AXI4-Lite interface.
- s_axis_ctrl_aresetn
- An active-Low reset for the AXI4-Stream control interface.
These signals are only present on the core boundary when the appropriate
interfaces are enabled. They only need to be asserted for a single clock cycle to take effect.
In addition, each AXI interface (<name>) you will have a reset singal
<name>_aresetn if ALWAYS_HAVE_AXI_CLK is 1, or the family is Versal.