Demonstration Test Bench - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)

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1.0 English

When the core is generated using the Vivado Design Suite, a demonstration test bench is created. This is a simple VHDL test bench that exercises the core.

The demonstration test bench source code is one VHDL file: demo_tb/tb_<component_name>.vhd in the Vivado output directory. The source code is comprehensively commented.