Per-Interface Port Descriptions - 1.0 English - PG375

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)

Document ID: PG375
Release Date: 2022-05-31
Version: 1.0 English

In the following table, <name> is a user-defined name for the interface being decoupled. For example, rp_<name>_data could be:

rp_fifo_data, where <name> = fifo.
rp_counter_data, where <name> = counter.

Table 1. Per-Interface Port Descriptions
Name	I/O	Description
rp_<name>_<signal>	I or O	A signal <signal> in interface <name> that is to be attached to the Reconfigurable Partition.
s_<name>_<signal>	I or O	A signal <signal> in interface <name> that is to be attached to the static logic.
<name>_aclk	I	Optional clock signal for AXI interfaces. Used by the IP integrator. Enabled when ALWAYS_HAVE_AXI_CLK is 1 or the family is Versal. If enabled, then it will be used for clock domain crossing (if required) and interface registering (if required).
<name>_arestn	I	Optional reset signal for AXI interfaces. Used by the IP integrator. Enabled when ALWAYS_HAVE_AXI_CLK is 1 or the family is Versal.
<name>_ref_clk	I	A reference clock for interface <name>. Automatically enabled when clock domain crossing is required for this interface and <name>_aclk is not enabled. Disabled otherwise.
<name>_decouple_status	O	The decouple status for interface <name>. Automatically enabled when clock domain crossing is required for this interface. Disabled otherwise.