If the clock used to generate signals for a decoupled interface is different from the clock that manages the decoupler's control interfaces, clock domain crossing can be enabled for that interface. When clock domain crossing is enabled, a reference clock input for the decoupled interface is added to the core's port map. This provides the clock to use for the secondary stages of the clock domain crossing synchronizer.
The clock for the primary stage of the clock domain crossing synchronizer is
the AXI clock if available. If the AXI clock is not present (because all of the AXI4-Stream and AXI4-Lite
interfaces are disabled), a reference clock called decouple_ref_clk is enabled on the port map, and that is used to clock the primary
stage of the clock domain crossing synchronizer.