Product Specification - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)

Document ID
Release Date
1.0 English

Designers of partially reconfigurable systems must consider several effects that can occur when reconfigurable modules are used.

Undesirable values driven into the static logic
Signals driven by resources in the Reconfigurable Partition that is undergoing reconfiguration might take on undesirable values, namely:
  • They might glitch.
  • They might be driven to 1 by the interconnect which is undesirable if the signal is an active-High control signal.
  • They might be driven by a Reconfigurable Module that has not been reset and is therefore in an unknown state.
Corruption of the new Reconfigurable Module
Signals driven by the static logic into the Reconfigurable Partition that is undergoing reconfiguration can cause the newly loaded Reconfigurable Module to become corrupted. For example:
  • Spurious writes to memories can occur.
  • Parts of the reconfigurable module can start to operate while other parts do not. This can occur even with RESET_AFTER_RECONFIG because the GWE (Global Write Enable) signal is asynchronous to the user clock, so it could write enable parts of the new Reconfigurable Module in one user clock cycle but leave other parts write disabled.

If any of these effects are problematic for a design, you can use decoupling logic to manage the signal values on the boundary between the static logic and the Reconfigurable Partition that is undergoing reconfiguration.

The signals that need to be decoupled are design-specific, and the following guidelines are recommended:

  • Decouple all control signals generated from the Reconfigurable Partition.
  • Decouple all control signals driven into the Reconfigurable Partition if the Reconfigurable Module being loaded cannot be fully reset before operation.
  • If a Reconfigurable Module has logic that can start to execute without being qualified by a decoupled control signal, consider decoupling the appropriate input clock.