|
Core Specifics |
| Supported Device Family
1
|
UltraScale+™
,
UltraScale™
,
Zynq®-7000 SoC, 7 series
|
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream
|
| Resources |
Performance and Resource Use web
page
|
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Not Provided |
| Test Bench |
VHDL |
| Constraints File |
Xilinx Constraints File (XDC) |
| Simulation Model |
Source HDL |
| Supported S/W Driver |
N/A |
| Tested Design
Flows
2
|
| Design Entry |
Vivado Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 73351
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
|