Clock and Reset Ports - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)
Document ID
PG375
Release Date
2022-05-31
Version
1.0 English
Table 1. Clock and Reset Ports
Name I/O Description
aclk I Rising-edge clock used for the AXI4-Lite and AXI4-Stream interfaces.
s_axi_reg_aresetn I Synchronous active-Low reset for the AXI4-Lite interface.