Clock Port Summary - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)

Document ID
PG375
Release Date
2022-05-31
Version
1.0 English

The following table enumerates all scenarios for an instance with an example AXI interface called intf. The Has AXI Clock column reflects the results of the following equation:

ALWAYS_HAVE_AXI_CLK OR (Family==Versal)
Table 1. Clock Port Summary
Has AXI status or control interfaces Has AXI Clock CDC Stages Register Interface Clock Used for IPI Only AXI Ctrl/Status Clock CDC Source Clock CDC Destination Clock Register Clock
0 0 0 0   - - - -
0 0 0 1   - - - decouple_ref_clk
0 0 2+ 0   - decouple_ref_clk intf_ref_clk -
0 0 2+ 1   - decouple_ref_clk intf_ref_clk intf_ref_clk
0 1 0 0 intf_aclk - - - -
0 1 0 1   - - - intf_aclk
0 1 2+ 0   - decouple_ref_clk intf_aclk -
0 1 2+ 1   - decouple_ref_clk intf_aclk intf_aclk
1 0 0 0   aclk - - -
1 0 0 1   aclk - - aclk
1 0 2+ 0   aclk aclk intf_ref_clk -
1 0 2+ 1   aclk aclk intf_ref_clk intf_ref_clk
1 1 0 0 intf_aclk aclk - - -
1 1 0 1   aclk - - intf_aclk
1 1 2+ 0   aclk aclk intf_aclk -
1 1 2+ 1   aclk aclk intf_aclk intf_aclk