Optional AXI4-Lite Register Ports - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)

Document ID
PG375
Release Date
2022-05-31
Version
1.0 English
Table 1. Optional AXI4-Lite Register Interface Ports
Name I/O Description
s_axi_reg_awaddr I 1-bit wide signal
s_axi_reg_awvalid I  
s_axi_reg_awready O  
s_axi_reg_wdata I 32-bit wide signal. Only bit 0 is used.
s_axi_reg_wvalid I  
s_axi_reg_wready O  
s_axi_reg_bresp O 2-bit wide signal.
s_axi_reg_bvalid O  
s_axi_reg_bready I  
s_axi_reg_araddr I 1-bit wide
s_axi_reg_arvalid I  
s_axi_reg_arready O  
s_axi_reg_rdata O 32-bit wide signal. Only bit 0 is used. Other bits return 0.
s_axi_reg_rresp O 2-bit wide signal.
s_axi_reg_rvalid O  
s_axi_reg_rready I