The control register contains the CPU ID and enables fault injection. This is write only register. Issuing a read request to the control register generates the read acknowledgment with zero data. The register bit assignment is shown in
Table: Control Register (CR)
and described in
Table: Control Register Bit Definitions
.
Table 2-46:
Control Register (CR)
|
Reserved
|
INJ
|
CPU
|
MAGIC
|
|
31
|
11
|
10
|
9
|
8
|
7
|
0
|
Table 2-47:
Control Register Bit Definitions
|
Bits
|
Name
|
Access
|
Reset
Value
|
Description
|
|
31-11
|
Reserved
|
N/A
|
0
|
Reserved
|
|
10
|
Interrupt Enabled
|
W
|
0
|
Enables fault injection. Automatically cleared after a fault has been injected:
0 = No fault is injected.
1 = Inject fault when AIR is equal to PC.
|
|
9-8
|
CPU ID
|
W
|
00
|
CPU identifier that must match parameter C_CPU_ID to enable injection.
|
|
7-0
|
Magic byte
|
W
|
0x00
|
Magic byte that must match parameter C_MAGIC to enable injection.
|