The single-string design is comprised of MicroBlaze™ with local memory, MDM, and an I/O Module configured to enable the UART.
create_project project_1 project_1 -part xcku040-ffva1156-3-e
create_bd_design benchmark
set mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze microblaze_0]
set_property -dict [list CONFIG.C_USE_BARREL 1 CONFIG.C_USE_HW_MUL 1 \
CONFIG.C_USE_MSR_INSTR 1 CONFIG.C_USE_PCMP_INSTR 1] $mb
apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config \
{local_mem "32KB" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0"
clk "New External Port (100 MHz)"} $mb
set io [create_bd_cell -type ip -vlnv xilinx.com:ip:iomodule iomodule_0]
set_property -dict [list CONFIG.C_USE_UART_RX 1 CONFIG.C_USE_UART_TX 1] $io
apply_bd_automation -rule xilinx.com:bd_rule:iomodule -config \
{processor "/microblaze_0"} $io
make_bd_pins_external [get_bd_pins $io/UART_Rx] [get_bd_pins $io/UART_Tx]
make_bd_pins_external [get_bd_pins rst_Clk_100M/ext_reset_in]
group_bd_cells tmr_0 $mb $io [get_bd_cells microblaze_0_local_memory]
assign_bd_address
regenerate_bd_layout
save_bd_design
Save the Tcl code listed here in a file named benchmark_1.tcl, and then use the following command to recreate the single-string design:
% vivado -source benchmark_1.tcl
When the single-string design has been created, the TMR Block Automation can be run to triplicate it by executing this Tcl code in the Vivado Tcl console:
validate_bd_design
create_bd_cell -type ip -vlnv xilinx.com:ip:tmr_manager:1.0 tmr_0/tmr_manager_0
apply_bd_automation -rule xilinx.com:bd_rule:tmr -config \
{bram "Local" wd "None" sem_if "External" sem_wd "1" brk "1" mask "0"
inject "0"} [get_bd_cells tmr_0/tmr_manager_0]
save_bd_design