This 32-entry-deep FIFO contains data transmitted to the SEM monitor. The FIFO bit definitions are shown in Table: Monitor Transmit Register (MON_TRANSMIT) . Data to be transmitted is written into this register. When a write request is issued while the FIFO is full, a bus error (SLVERR) is generated and the data is not written into the FIFO. This is a write-only location. Issuing a read request to the transmit data FIFO generates the read acknowledgment with zero data. Table: Monitor Transmit FIFO Register Bit Definitions shows the location for data on the AXI interface. The register is only implemented if C_INTERFACE is set to 0.