SEM Interrupt Mask Register (SEMIMR)

SEM Interrupt Mask Register (SEMIMR) - 1.0 English

MicroBlaze Triple Modular Redundancy (TMR) Subsystem (PG268)

Document ID

PG268

Release Date

2022-04-28

Version

1.0 English

The SEM interrupt mask register enables interrupt generation from signals from the TMR SEM interface. This is a write only register.Issuing a read request generates the read acknowledgment with zero data. The register bit assignment is shown in Table: SEM Interrupt Mask Register (SEMIMR) and described in Table: SEM Interrupt Mask Register Bit Definitions . The register is only implemented if C_SEM_INTERFACE is set to 1.

Table 2-38: SEM Interrupt Mask Register (SEMIMR)
Reserved		DS	DO	ESS	UNC	INJ	CLA	CORR	OBS	INI	HB	HBWE
31	11	10	9	8	7	6	5	4	3	2	1	0

Table 2-39: SEM Interrupt Mask Register Bit Definitions
Bits	Name	Access	Description
31-11	Reserved	N/A	Reserved
10	Diagnostic Scan	R	The SEM Diagnostic Scan input causes an interrupt.
9	Detect Only	R	The SEM Detect Only input causes an interrupt.
8	Essential	R	The SEM Essential input causes an interrupt.
7	Uncorrectable	R	The SEM Uncorrectable input causes an interrupt.
6	Injection	R	The SEM Injection input causes an interrupt.
5	Classification	R	The SEM Classification input causes an interrupt.
4	Correction	R	The SEM Correction input causes an interrupt.
3	Observation	R	The SEM Observation input causes an interrupt.
2	Initialization	R	The SEM Initialization input causes an interrupt.
1	Heartbeat	R	The SEM Heartbeat input causes an interrupt.
0	Heartbeat Watchdog Expired	R	The SEM heartbeat watchdog causes an interrupt: 0 = No interrupt. 1 = An interrupt occurs when the watchdog expires.