The SEM status register contains the status signals from the TMR SEM core. This is a read only register. If a write request is issued to the SEM status register it does nothing but generate a write acknowledgment. The register bit assignment is shown in Table: SEM Status Register (SEMSR) and described in Table: SEM Status Register Bit Definitions . The register is only implemented if C_SEM_INTERFACE is set to 1.
Reserved |
DS |
DO |
ESS |
UNC |
INJ |
CLA |
CORR |
OBS |
INI |
HB |
HBWE |
|
31 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |