Revision History - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)

Document ID
Release Date
1.0 English
Section Revision Summary
06/03/2022 Version 1.0
General updates
05/22/2019 Version 1.0
Unsupported Features Updated section.
04/04/2018 Version 1.0
General Updates Updated to reflect the Gen4 supports -2L speed grade.
10/04/2017 Version 1.0
Port Descriptions
  • Added GT Specific Ports for Ultrascale+ Devices only figure.
  • Updated the ASPM Support Option and added GT Channel DRP option to the Advanced Setting Tab in the IP Customization Dialog Box.
IP Facts Minor editorial changes.
04/05/2017 Version 1.0
General Updates Updated Device Utilization – Ultrascale+ Devices table.
10/05/2016 Version 1.0
General Updates
  • Updated for support of Gen 1, Gen 2, and Gen3 speeds in UltraScale devices, and Gen1, Gen2, Gen3, and Gen4 speeds in UltraScale+ devices.
  • Updated to include the supported KU115 UltraScale devices.
  • Updated to reflect the UltraScale devices also support 16.0 GT/s link speeds.
Performance and Resource Use Updated section.
Product Specification Added new Assist Signals table.
Design Flow Steps
  • Added that the limited supported target devices can be migrated easily to other devices.
  • Added the Spec 0.7 EIEOS Change Enable parameter, and update the Basic Tab figure.
  • Added the ASPM Support Option parameter, and updated the Advanced Settings Tab figure.
06/08/2016 Version 1.0
General Updates Added UltraScale architecture.
IP Facts Updated Features section.
Overview Updated description.
Feature Summary Updated table.
Port Descriptions Added TX, RX Data Signals for UltraScale, and Assist Signal tables
Clocking Updated section.
Customizing and Generating the Core Updated section.
Constraining the Core Added note to Required Constraints section.
04/15/2016 Version 1.0
IP Facts Product Specification Minor editorial changes.
04/06/2016 Version 1.0
Initial release. N/A