| LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
UltraScale+™ , UltraScale™ |
| Supported User Interfaces | N/A |
| Resources | Performance and Resource Use |
| Provided with Core | |
| Design Files | Verilog |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | Xilinx® Design Constraints (XDC) |
| Simulation Model | Verilog |
| Supported S/W Driver | N/A |
| Tested Design Flows 2 | |
| Design Entry | Vivado® Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 66988 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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