Command Signals Interface Ports - 1.0 English

Table 1. Command Signals
Port Name	Width	I/O	Clock Domain	Description
phy_txdetectrx	1	Input	pclk	Tells the PHY to perform receiver detection when this signal is logic High and POWERDOWN is in P1 low power state. Receiver detection is complete when phystatus asserts for one pclk cycle. The status of receiver detection is indicated in rxstatus when phystatus is logic High for one pclk cycle. rxstatus = 000b: Receiver not Present rxstatus = 001b: Receiver Present
phy_txelecidle	1	Input	pclk	Forces the tx[p/n] to electrical idle when this signal is logic High. During electrical idle, tx[p/n] are driven to the DC common mode voltage. Per-lane.
phy_txcompliance	1	Input	pclk	Sets the running disparity to negative when this signal is logic High. Used when transmitting the PCIe compliance pattern. Per-lane.
phy_rxpolarity	1	Input	pclk	Requests the PHY to perform polarity inversion on the received data when this signal is logic High. Per-lane.
phy_powerdown[1:0]	2	Input	pclk	Request PHY to enter power saving state or return to normal power state. Power management is complete when PHYSTATUS asserts for one PCLK cycle. 00b: P0, normal operation. 01b: P0s, power saving state with low recovery time latency. 10b: P1, power saving state with longer recovery time latency. 11b: P2, lowest power state. P2 not supported.
phy_rate[2:0]	3	Input	pclk	Request the PHY to perform a dynamic rate change. Rate change is complete when PHYSTATUS asserts for one PCLK cycle. rxvalid, rxdata, and rxstatus must be ignored while the PHY is in rate change. For Versal premium device, 3 bits are valid, while only 2 bits are valid for Versal prime. Versal prime 00b: Gen1 01b: Gen2 10b: Gen3 11b: Gen4 Versal premium 000b: Gen1 001b: Gen2 010b: Gen3 011b: Gen4 1xxb: Gen5 In the simulation mode (PHY_SIM_EN = TRUE), PHY status assertion takes about 45 us for Gen3 speed change.

Command Signals Interface Ports - 1.0 English - PG239

PCI Express PHY LogiCORE IP Product Guide (PG239)