PCI Express®
PHY IP GTH/GTY can be configured to support
PCIe®
applications with 100 MHz, 125 MHz, or 250 MHz reference clock.
The reference clock can be synchronous or asynchronous.
The phy_pclk is the primary clock for the PIPE interface,
FPGA fabric, and GTH/GTY [TX/ RX] usrclk and [TX/RX]
usrclk2.
In addition to phy_pclk, two
other clocks (phy_coreclk and phy_userclk ) are available to support the PCIe MAC
BUFG_GTs are used to generate these
clocks, so MMCM is not required.
The source of the GTH/GTY reference clock must come
directly from IBUFDS_GTE4 for UltraScale+
devices and from IBUDS_GTE3 for UltraScale
devices.
To use the reference clock for FPGA fabric, another BUFG_GT must be used.
The gt_gtpowergood
output port of the PCIe PHY IP must drive the CE
pin of BUFG_GT.
The following figure shows an x2 PCIe architecture example.
Figure 1. Clock Architecture
For more information on PHY IP Clocking, refer to the
Clocking section in the UltraScale+
Devices Integrated Block for PCI Express LogiCORE IP Product
Guide (PG213).