Port Descriptions - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)

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The following tables describe the supported PIPE signals by the PCIe PHY IP. For additional details, refer to the PIPE specification. The signals described in this section are based on a single lane application. Signals can be per-lane, or per-design. If not indicated in the description, the default is per-design. Per-design indicates that one signal controls all lanes (0 to N-1 Lane).

A per-lane signal on the PCIe PHY IP is in a form of {LaneN-1[Width-1:0], …Lane1 [Width-1:0], Lane0[Width-1:0]}.

The Gen3/Gen4 TX and RX equalization defined here is different from the PIPE specification. The custom Gen3/Gen4 equalization scheme described here must be used. For more details, refer to Equalization Sequences.

Assist signals are used to support the functionality of PCIe PHY IP according to the MAC LTSSM states.