Performance and Resource Use - 1.0 English

PCI Express PHY LogiCORE IP Product Guide (PG239)
Document ID
PG239
Release Date
2022-06-03
Version
1.0 English

Resources required for the PCIe PHY IP are mentioned in the table below. These values are generated using Vivado® Design Suite for the supported devices.

Table 1. Device Utilization – UltraScale+ Devices
Family Speed Lane XCVU3P/XCZU9EG
LUTs FFs LUT-FF Pairs
UltraScale+ Gen1 x1 118 264 89
Gen2 x1 117 268 87
Gen3 x1 116 268 74
Gen4 x1 340 615 288
Gen1 x2 215 496 161
Gen2 x2 216 496 159
Gen3 x2 216 496 148
Gen4 x2 655 1195 555
Gen1 x4 406 960 304
Gen2 x4 406 952 297
Gen3 x4 408 952 296
Gen4 x4 1284 2339 1075
Gen1 x8 790 1888 579
Gen2 x8 796 1868 569
Gen3 x8 796 1868 592
Gen4 x8 2537 4633 2149
Gen1 x16 1601 3744 1158
Gen2 x16 1606 3700 1201
Gen3 x16 1606 3700 1168
Table 2. Device Utilization – UltraScale Devices
Family Speed Lane XCVU440/XCKU040 – Production Part XCVU440 -ES2 Part
LUTs FFs LUT-FF Pairs LUTs FFs LUT-FF Pairs
UltraScale Gen1 x1 104 222 77 304 459 200
Gen2 x1 107 226 77 306 462 204
Gen3 x1 106 226 79 308 463 202
Gen1 x2 176 393 128 606 893 390
Gen2 x2 177 389 129 608 893 388
Gen3 x2 177 389 126 607 893 379
Gen1 x4 315 735 228 1,182 1,761 748
Gen2 x4 317 715 221 1,188 1,761 760
Gen3 x4 316 715 227 1,188 1,753 764
Gen1 x8 591 1419 419 2,357 3,497 1,505
Gen2 x8 593 1371 431 2,357 3,497 1,508
Gen3 x8 592 1371 422 2,343 3,476 1,488
  1. No DSP48s/36k block RAMs/18k block RAMs were used in the PCIe PHY IP.