Basic Tab - 1.0 English - PG239

PCI Express PHY LogiCORE IP Product Guide (PG239)
Document ID
PG239
Release Date
2024-12-18
Version
1.0 English

The initial customization screen is used to define the basic parameters for the core, including the component name, reference clock frequency, lane width, and speed.

Figure 1. Basic Tab
Component Name
It is the base name of the output files generated for the core. The name must begin with a letter and can be composed of these characters: a to z, 0 to 9, and "_."
Link Width
The core requires the selection of the initial lane width. Supported lane widths are x1, x2, x4, x8, and x16 ( AMD UltraScale+™ devices only).
Maximum Link Speed
The core allows you to select the Maximum Link Speed supported by the device. Supported link speeds are:
  • 2.5 Gb/s, 5.0 Gb/s, and 8.0 Gb/s for UltraScale devices.
  • 2.5 Gb/s, 5.0 Gb/s, 8.0 Gb/s and 16.0 Gb/s for UltraScale+ devices.
Input Reference Clock Frequency
Selects the input frequency of the reference clock provided on sys_clk. It is the GT REFCLK frequency for the IP. Supported values are 100 MHz, 125 MHz, and 250 MHz. For important information about clocking, see Clocking.
Output User Clock Frequency
Selects the frequency of the output USERCLK that can be used by the PCIe MAC.
Table 1. User Clock Options
Speed Lane UltraScale+ User Clock (in MHz) UltraScale User Clock (in MHz)

Gen1

 x1 62.5, 125, 250 62.5, 125, 250
x2 62.5, 125, 250 62.5, 125, 250
x4 62.5, 125, 250 125, 250
x8 62.5, 125, 250 125, 250
x16 62.5, 125, 250 N/A

Gen2

 x1 62.5, 125, 250 62.5, 125, 250
x2 62.5, 125, 250 125, 250
x4 62.5, 125, 250 125, 250
x8 62.5, 125, 250 125, 250
x16 62.5, 125, 250 N/A

Gen3

 x1 62.5, 125, 250 125, 250
x2 62.5, 125, 250 125, 250
x4 62.5, 125, 250 125, 250
x8 62.5, 125, 250 250
x16 62.5, 125, 250, 500 N/A

Gen4

 x1 125, 250 N/A
x2 125, 250 N/A
x4 125, 250 N/A
x8 125, 250, 500 N/A
For important information about clocking the core, see Clocking.
Output Core Clock Frequency
Selects the frequency of the output coreclk that can be used by the PCIe MAC. 250 MHz is supported for all configurations. In UltraScale+ devices, there is support for 500 MHz for x16 Gen3 (8.0 Gb/s) and for x8 Gen4 (16.0 Gb/s) configurations. For important information about clocking the core, see Clocking.
PLL Type
Selects the PLL type for GTs used. For Gen2 speed, select between CPLL and QPLL1. For Gen1 speed, PLL type is fixed to CPLL, for Gen3 speed it is fixed to QPLL1 and for Gen4 speed it is fixed to QPLL0.
Table 2. PLL Type
Link Speed PLL Type Description
2.5 GT/s CPLL The default is CPLL and not available for selection.
5.0 GT/s QPLL1, CPLL The default is QPLL1 and not available for selection.
8.0 GT/s QPLL1 The default is QPLL1 and not available for selection.
16.0 GT/s QPLL0 The default is QPLL0 and not available for selection.
PIPE Interface pipeline registers
Selects the number of pipeline stages in the PIPE interface. Supported values are 0, 1, 2, and 3.
Spec 0.7 EIEOS Change Enable
Enables the EIEOS support feature from the v0.7 Spec for PCIe Gen4. This option is only available for UltraScale+ devices (except AMD Zynq™ UltraScale+ ES1 Silicon parts).