The block RAMs are configurable to various port widths and sizes. Depending on the configuration, some data pins and address pins are not used. Table 1 through Table 4 show the pins used in various configurations. In addition to the information in these tables, these rules are useful to determine the RAMB port connections:
- When using RAMB36E5, if the DIN[A|B] pins are less than 32 bits wide, concatenate (32 - DIN_BIT_WIDTH) logic zeros to the front of DIN[A|B].
- If the DINP[A|B] pins are less than 4 bits wide, concatenate (4 - DINP_BIT_WIDTH) logic zeros to the front of DINP[A|B]. DINP[A|B] can be left unconnected when not in use.
- DOUT[A|B] pins must be 32 bits wide. However, valid data are only found on pins DOUT_BIT_WIDTH – 1 down to 0.
- DOUTP[A|B] pins must be 4 bits wide. However, valid data are only found on pins DOUTP_BIT_WIDTH – 1 down to 0. DOUTP[A|B] can be left unconnected when not in use.
- For the RAMB18E5, ADDR[A/B] is 11 bits wide and for the RAMB32E5, ADDR[A/B] is 12 bits wide. Address width is defined in Table 1.