Inverting Control Pins

Versal ACAP Memory Resources Architecture Manual (AM007)

Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

For each port, the eight control pins (CLK, EN, ARST, RSTREG, and RSTRAM) each have an individual inversion option. EN, RSTREG, and RSTRAM control signals can be configured as active-High or Low, and the clock can be active on a rising or falling edge (active-High on rising edge by default), without requiring other logic resources.