Dual Port SRAM Array Operations

The dual-port 288 Kb UltraRAM consists of a 288 Kb storage area and two independent access ports, A and B. Both ports share a single clock input.

In each clock cycle, each port can perform either a read or a write operation independent of the other port. Any combination of read/write is allowed on any of the two ports. The read and write operations are always synchronous to the clock. The operation of port A is always executed first followed by the operation of port B within the same clock cycle. Consequently, data access collision is not possible when both ports access the same address locations. Each port has its own address, data in, data out, enable, and write enable.

• If both ports are executing read and write for the same address, the behavior is defined as (see the following table):
  • If port A is writing, port B is reading, then port B reads new data.
  • If port A is reading, port B is writing, then port A reads the old data.
  • If port A and B are writing, then port B write overwrites the port A write. At the end of the clock cycle, the memory stores port B write data.