The 26-bit address bus selects the memory cells for read or write. The upper 11 address bits (ADDR[25:15]) select the UltraRAM instance from a cascaded set of UltraRAM when multiple UltraRAM are cascaded in a deep memory array formation. To identify the selected UltraRAM instance in a cascaded set, each UltraRAM has a built-in comparator which compares the upper 11-bit address with a unique SELF_ADDR attribute. The SELF_MASK attribute defines how many of the 11-bit addresses should be used for the compare.
The lower 15 address bits (ADDR[14:0]) select the data from a single UltraRAM or from the selected UltraRAM in a cascaded set. The port data width affects the depth of the UltraRAM, and the depth determines which of the lower 15 address bits are used for data selection. One or more of the least significant address bits are not used for port data widths wider than 9 bits. See the following table for the port address bits used in data selection versus the port data width.
| Port Data Width | Effective Port Address Width | Depth | ADDR Bus 1 |
DIN Bus DOUT Bus |
BWE 2 |
|---|---|---|---|---|---|
| PARITY_INDEPENDENT Mode | |||||
| 72 | 23 | 4,096 | [25:3] | [71:0] | [8:0] |
| PARITY_INTERLEAVED Mode | |||||
| 72 | 23 | 4,096 | [25:3] | [71:0] | [7:0] |
| 36 | 24 | 8,192 | [25:2] | [35:0] | [3:0] |
| 18 | 25 | 16,384 | [25:1] | [17:0] | [1:0] |
| 9 | 26 | 32,768 | [25:0] | [8:0] | [0] |
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