- Support for bit widths x1, x2, x4 has been removed.
- The default port width has changed to 0 for RAMB36 and RAMB18.
- Hard FIFO support is removed. Fabric logic can be used to implement FIFO
functions.
- Address enable/compare feature is removed.
- Systolic cascade support has been removed.
- SRVAL/INIT attributes are merged into a single attribute.
- Async reset on the output registers is supported.
- Byte write mode parity interleaved and parity independent (x72).
- The ADDREN pin has been removed.
- The CASDIMUX pins have been removed.
- The ECCPARITY[7:0] pins have been removed.
- RDADDRECC[8:0] has been removed.
- Support for an asynchronous reset to logic 0 for the output register has been
added:
- A new attribute RST_MODE has been added to support this feature.
- Additional pins ARST_A and ARST_B have been added.
- An extra bit WEBWE[8] was added to the WEBWE bus to support a separate parity byte
write enable in x72 mode:
- A new attribute BWE_MODE_B supports this feature.