This table lists and describes the block RAM ECC-related I/O port names.
| Port Name | Signal Description |
|---|---|
| INJECTSBITERR | Injects a single-bit error if ECC is used. Creates a single-bit error at a particular block RAM bit location when asserted during write. The block RAM ECC logic corrects this error when this location is read back. The error is created in bit DIN[30]. |
| INJECTDBITERR | Injects a double-bit error if ECC is used. Creates a double-bit error at two particular block RAM bit locations when asserted during write. The block RAM ECC logic flags a double-bit error when this location is read back. When both INJECTSBERR and INJECTDBERR signals are simultaneously asserted, a double-bit error is injected. The errors are created in bits DIN[30] and DIN[62]. |
| SBITERR | ECC single-bit error output status. See also the dedicated cascade pins in this table when using the block RAM in ECC cascade mode.(1) |
| DBITERR | ECC double-bit error output status. See also the dedicated cascade pins in this table when using the block RAM in ECC cascade mode.(1) |
| CASINSBITERR | ECC single-bit error input in cascade mode. Cascade SBERR error bit status from the previous block RAM. |
| CASOUTSBITERR | ECC single-bit error output in cascade mode. Cascade SBERR error bit status to the next block RAM. |
| CASINDBITERR | ECC double-bit error input in cascade mode. Cascade DBERR error bit status from the previous block RAM. |
| CASOUTDBITERR | ECC double-bit error output in cascade mode. Cascade DBERR error bit status to the next block RAM. |
| ECCPIPECE | ECC pipeline register clock enable when EN_ECC_PIPE = TRUE. This is available only in ECC mode when EN_ECC_READ = TRUE. |
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