Data-In Buses – DIN_A, DIN_B

Versal ACAP Memory Resources Architecture Manual (AM007)
Document ID
AM007
Release Date
2020-11-24
Revision
1.1 English

Data-in buses provide the new data value to be written into UltraRAM. The data bus is 72-bits wide with the lower 64 bits used for data and the upper 8 bits used for parity or for regular data inputs.

Table 1. Byte Write Enable (URAM288E5)
BWE_MODE_A/B BWE_A/B DIN_A/B
Parity Interleaved Mode
PARITY_INTERLEAVED BWE_A/B[7] DIN_A/B[71,63:56]
PARITY_INTERLEAVED BWE_A/B[6] DIN_A/B[70,55:48]
PARITY_INTERLEAVED BWE_A/B[5] DIN_A/B[69,47:40]
PARITY_INTERLEAVED BWE_A/B[4] DIN_A/B[68,39:32]
PARITY_INTERLEAVED BWE_A/B[3] DIN_A/B[67,31:24]
PARITY_INTERLEAVED BWE_A/B[2] DIN_A/B[66,23:16]
PARITY_INTERLEAVED BWE_A/B[1] DIN_A/B[65,15:8]
PARITY_INTERLEAVED BWE_A/B[0] DIN_A/B[64,7:0]
Parity Independent Mode
PARITY_INDEPENDENT BWE_A/B[8] DIN_A/B[71:64]
PARITY_INDEPENDENT BWE_A/B[7] DIN_A/B[63:56]
PARITY_INDEPENDENT BWE_A/B[6] DIN_A/B[55:48]
PARITY_INDEPENDENT BWE_A/B[5] DIN_A/B[47:40]
PARITY_INDEPENDENT BWE_A/B[4] DIN_A/B[39:32]
PARITY_INDEPENDENT BWE_A/B[3] DIN_A/B[31:24]
PARITY_INDEPENDENT BWE_A/B[2] DIN_A/B[23:16]
PARITY_INDEPENDENT BWE_A/B[1] DIN_A/B[15:8]
PARITY_INDEPENDENT BWE_A/B[0] DIN_A/B[7:0]