You can construct memories and FIFOs in the programmable logic with block RAMs using the Vivado IP integrator block design flow. You can infer block RAMs during high-level synthesis or synthesis of VHDL or Verilog code. You can also explicitly instantiate and initialize block RAMs in VHDL or Verilog code.
You can construct single- or dual-port memories with UltraRAMs that are instantiated and initialized to user-defined values in VHDL or Verilog code. You can also infer UltraRAMs during synthesis from VHDL or Verilog code. Refer to the Vivado Design Suite User Guide: Synthesis (UG901) for RAM HDL coding techniques.