- CASCADE_ORDER_A/B determines the UltraRAM block cascade order for
control and data.
- NONE (Default) – UltraRAM is not in cascade mode.
- FIRST – UltraRAM is the first instance in a cascade chain in each column of the chain.
- MIDDLE – UltraRAM is a the middle instance in a cascade chain.
- LAST – UltraRAM is the last instance in a cascade chain in each column of the chain.
For legal combinations of cascade order attributes, see Table 1.
- SELF_MASK_A/B[25:15] determines the number of UltraRAM blocks in the
cascade chain and therefore which of the ADDR_A/B[22:12] bits are used.
-
11'h7ff(Default) – Not in cascade mode. ADDR_A/B[25:15] inputs are masked. -
11'h7fe– 2 UltraRAMs are cascaded. ADDR_A/B[25:16] inputs are masked. -
11'h7fc– 3-4 UltraRAMs are cascaded. ADDR_A/B[25:17] inputs are masked -
11'h7f8– 5-8 UltraRAMs are cascaded. ADDR_A/B[25:18] inputs are masked. -
11'h7f0– 9-16 UltraRAMs are cascaded. ADDR_A/B[25:19] inputs are masked. -
11'h7e0– 17-32 UltraRAMs are cascaded. ADDR_A/B[25:20] inputs are masked. -
11'h7c0– 31-64 UltraRAMs are cascaded. ADDR_A/B[25:21] inputs are masked. -
11'h780– 65-128 UltraRAMs are cascaded. ADDR_A/B[25:22] inputs are masked. -
11'h700– 129-256 UltraRAMs are cascaded. ADDR_A/B[25:23] inputs are masked. -
11'h600– 257-512 UltraRAMs are cascaded. ADDR_A/B[25:24] inputs are masked. -
11'h400– 513-1024 UltraRAMs are cascaded. ADDR_A/B[25] input is masked. -
11'h000– 1025-2048 (1036) UltraRAMs are cascaded. None of the address inputs are masked.
-
- SELF_ADDR_A/B[25:15]
This attribute is used in cascade mode and must be set depending on which address bit in the UltraRAM cascade chain addresses the particular block to which it is attached. A particular UltraRAM block in the cascade chain is accessed when the self-address bit is set after masking with the address bits with the SELF_MASK_A/B attribute that matches the used ADDR_A/B address bits. The default is
11'h0(see the following figure).
Figure 1. Cascade Chain Examples
Note: SELF_ADDR/SELF_MASK can be used even
when CASCADE_ORDER_CTRL is set to NONE. This allows non-contiguous UltraRAMs to be
cascaded using fabric logic if needed. Typically SELF_MASK | SELF_ADDR is unique for all
the UltraRAMs in a cascade chain. This is a requirement for a read port to ensure the
correct read data propagated to the exit point.