Reset - 2022.1 English

MicroBlaze Processor Embedded Design User Guide (UG1579)

Document ID
Release Date
2022.1 English
  • Specify MSR Reset Value: Specify reset value for select MSR bits.
    • Setting ICE (=0x0020) enables instruction cache at reset.
    • Setting DCE (=0x0080) enables data cache at reset.
    • Setting EIP (=0x0200) sets exception in progress at reset.
    • Setting EE (=0x0100) enables exceptions at reset.
    • Setting BIP (=0x0008) sets break in progress at reset.
    • Setting IE (=0x0002) enables interrupts at reset.
    Tip: Enabling caches at reset will allow execution to start immediately from external memory and can thus be used to reduce or eliminate the need for LMB memory.