MicroBlaze Processor Constraints - 2022.1 English

MicroBlaze Processor Embedded Design User Guide (UG1579)

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2022.1 English

The IP integrator generates constraints for IP generated within the tool during output products generation; however, you must generate constraints for any custom IP or higher-level code.

A constraint set is a set of XDC files that contain design constraints, which you can apply to your design. There are two types of design constraints:

  • Physical constraints define pin placement, and absolute, or relative placement of cells such as: block RAMs, LUTs, Flip-Flops, and device configuration settings.
  • Timing constraints, written in industry standard SDC, define the frequency requirements for the design. Without timing constraints, the Vivado Design Suite optimizes the design solely for wire length and routing congestion.
    Note: Without timing constraints, Vivado implementation makes no effort to assess or improve the performance of the design.
    Important: The Vivado Design Suite does not support UCF format. For information on migrating UCF constraints to XDC commands see the ISE to Vivado Design Suite Migration Guide (UG911) for more information.

The options on how to use constraint sets, are, as follows:

  • Multiple constraints files within a constraint set.
  • Constraint sets with separate physical and timing constraint files.
  • A master constraints file, and direct design changes to a new constraints file.
  • Multiple constraint sets for a project, and make different constraint sets active for different implementation runs to test different approaches.
  • Separate constraint sets for synthesis and for implementation.
  • Different constraint files to apply during synthesis, simulation, and implementation to help meet your design objectives.

Separating constraints by function into different constraint files can make your overall constraint strategy more clear, and facilitate being able to target timing and implementation changes.

Organizing design constraints into multiple constraint sets can help you do the following:

  • Target different Xilinx FPGAs for the same project. Different physical and timing constraints could be necessary for different target parts.
  • Perform "what-if" design exploration. Using constraint sets to explore different scenarios for floorplanning and over-constraining the design.
  • Manage constraint changes. Override master constraints with local changes in a separate constraint file.
    Tip: A good way to validate the timing constraints is to run the report_timing_summary command on the synthesized design. Problematic constraints must be addressed before implementation.

For more information on defining and working with constraints that affect placement and routing, see the Vivado Design Suite User Guide: Using Constraints (UG903).