Instantiate MicroBlaze IP Cores - 2022.1 English

MicroBlaze Processor Embedded Design User Guide (UG1579)

Document ID
Release Date
2022.1 English

Create a block design and instantiate two instances of MicroBlaze IP as shown. Note that the Run Block Automation link becomes active in the banner.

Figure 1. Multiple MicroBlaze Instances in a Block Design

Click the Run Block Automation link to run block automation on both the MicroBlaze instances. Again, the options here varies on the design requirements.

For example:

  • Both the MicroBlaze processors might run from a single system clock or they could be totally independent.
  • They could share the Clocking Wizard IP or they could have independent Clocking Wizard IP.

This topology shows two independent Clocking Wizard IP for each MicroBlaze processor as in the following figure.

Figure 2. Block Automation Dialog Box for Dual MicroBlaze Design

The block design looks as shown in the following figure:

Figure 3. Block Design After Running Block Automation

Note: Both the MicroBlaze processors share the same MicroBlaze Debug Module that is automatically configured to support two debug interfaces.

At this point you can add peripherals to your design as needed. In this case, two instances of AXI UART Lite, one GPIO and a AXI blcok RAM Controller were added.

  • The AXI UART Lite IP is connected to each of the MicroBlaze processor instances.
  • The GPIO is connected to one instance of the MicroBlaze IP.
  • Finally, the AXI BRAM Controller controlling the Block Memory Generator is shared by both MicroBlaze processors.
  • The input clock to one of the Clocking Wizard IP is the on-board System Differential Clock while the other Clocking Wizard is tied to the on-board PCIe Clock.