MicroBlaze Design with a Memory IP Core - 2022.1 English

MicroBlaze Processor Embedded Design User Guide (UG1579)

Document ID
Release Date
2022.1 English

The Memory IP core provides a user clock (ui_clock) and up to five additional clocks (four in case of UltraScale Memory IP) that can be used in the rest of the design. You can configure the connection, as follows:

  1. When using the platform board flow automation in a design that contains the Memory IP, add the Memory IP first (or drag and drop the DDR3 SDRAM/DDR4 SDRAM interface from the Board window which instantiates the Memory IP core and configures it for the board), and then run Block Automation. This connects the on-board clock to the Memory IP core.

    You can then customize Memory IP to generate additional clocks, as shown in the following figure.

  2. After configuring the MIG to generate additional clocks, click the Run Connection Automation link at the top of the banner.

    The Run Connection Automation dialog box states that the ddr3_sdram interface is available, as shown in the following figure.

  3. Click OK.

    This connects the interface ports to the Memory IP, as shown in the following figure.

  4. Add the MicroBlaze processor to the design and run Block Automation, as shown in the following figure.

  5. In the Clock Connection field of the Run Block Automation dialog box, select the Memory IP ui_clk (/mig_7series_0/ui_clk or mig_7series/u_addn_clk_0) as the clock source for the MicroBlaze processor, as shown in the following figure, and click OK.
    Tip: The mig_7series_0/ui_addn_clk_0 is selected by default.

    This creates a MicroBlaze subsystem and connects the ui_addn_clk_0 as the input source clock to the subsystem, as shown by the highlighted net in the following figure.

  6. Make the following additional connections:
    1. Click Connection Automation and select /mig_7series/S_AXI to connect the Memory IP to MicroBlaze.
    2. In the Run Connection Automation dialog box select /microblaze_0 (Cached) option for the S_AXI interface.
    3. Leave all other settings for S_AXI to their default value of Auto.

    4. Connect the on-board reset to the sys_rst input of the Memory IP.
    5. Connect the ext_reset_in of the rst_mig_7_series_0_100M Processor System Reset block to reset (FPGA Reset).
    6. Click OK.

      The following figure shows the completed connection for MB-Memory IP with Designer Assistance.