Once a design has been implemented and the bitstream generated, you can export the design to the Vitis software platform for software application development. In rare cases where the Processing Logic does not contain any logic at all, you can also export the design without implementing or generating the bitstream.
To export your design, perform the following:
- From the Vivado File menu, select
.
The Export Hardware dialog box opens.
- Select the Include bitstream
option using the radio button in the Output view and click Next.
- Leave the XSA file name field at its default value and click
Next. (The following figure shows
Windows-specific settings.)
- Click Finish. This will
export the hardware XSA File in the project directory.
- After the hardware definition has been exported, select to launch the Vitis software
platform from Vivado.
The Eclipse Launcher dialog box opens, as shown in the following figure.
The Workspace field should be populated with the name of the directory where the software application project is to be created.
After you export the hardware definition to the Vitis software platform, and launch, you can start writing your software application.
You can perform further debug and software download from the Vitis software platform.
Alternatively, you can import the ELF file for the software back into the Vivado tools, and integrate it with the FPGA bitstream for further download and testing.