Registered AXI4-Stream Interfaces - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)
Document ID
UG1399
Release Date
2021-12-15
Version
2021.2 English

As a default, AXI4-Stream interfaces are always implemented as registered interfaces to ensure that no combinational feedback paths are created when multiple HLS IP blocks with AXI4-Stream interfaces are integrated into a larger design. For AXI4-Stream interfaces, four types of register modes are provided to control how the interface registers are implemented:

Forward
Only the TDATA and TVALID signals are registered.
Reverse
Only the TREADY signal is registered.
Both
All signals (TDATA, TREADY, and TVALID) are registered. This is the default.
Off
None of the port signals are registered.

The AXI4-Stream side-channel signals are considered to be data signals and are registered whenever TDATA is registered.

Recommended: When connecting HLS generated IP blocks with AXI4-Stream interfaces at least one interface should be implemented as a registered interface or the blocks should be connected via an AXI4-Stream Register Slice.

There are two basic methods to use an AXI4-Stream in your design:

  • Use an AXI4-Stream without side-channels.
  • Use an AXI4-Stream with side-channels.

This second use model provides additional functionality, allowing the optional side-channels which are part of the AXI4-Stream standard, to be used directly in your C/C++ code.