DATAFLOW optimization is a dynamic optimization which
can only be fully understood after the RTL co-simulation is complete. Due to this fact, the
Dataflow viewer lets you see the dataflow structure inferred by the tool, inspect the channels
(FIFO/PIPO), and examine the effect of channel depth on performance. Performance data is
back-annotated to the Dataflow viewer from the co-simulation results.You must apply the DATAFLOW pragma or directive to your
design for the Dataflow viewer to be populated. You can apply dataflow to the top-level
function, or specify regions of a function, or loops. The Dataflow viewer displays a
representation of the dataflow graph structure, showing the different processes and the
underlying producer-consumer connections.
In the Module Hierarchy view, the
icon beside the
function indicates that a Dataflow Viewer report is available. When you see this icon, you can
right-click the function and use the Open Dataflow
Viewer command.
Features of the Dataflow viewer include the following:
- Source Code browser.
- Automatic cross-probing from process/channel to source code.
- Filtering of ports and channel types.
- Process and Channel table details the characteristics of the design:
- Channel Profiling (FIFO sizes etc), enabled from Solution Settings dialog box.
- Process Read Blocking/Write Blocking/Stalling Time reported after RTL
co-simulation.Important: You must use
cosim_design -enable_dataflow_profilingto capture data for the Dataflow viewer, and your test bench must run at least two iterations of the top-level function. - Process Latency and II displayed.
- Channel type and widths are displayed in the Channel table.
- Automatic cross-probing from Process and Channel table to the Graph and Source browser.
- Hover over channel or process to display tooltips with design information.
The Dataflow viewer can help with performance debugging your designs. When your design deadlocks during RTL co-simulation, the GUI will open the Dataflow viewer and highlight the channels and processes involved in the deadlock so you can determine if the cause is insufficient FIFO depth, for instance.
When your design does not perform as expected, the Process and Channels table can help you understand why. A process can stall waiting to read input, or can stall because it cannot write output. The channel table provides you with stalling percentages, as well as identifying if the process is "read blocked" or "write blocked."