s_axilite interface. The register map, which
is added to the generated RTL files, can be divided into two sections:- Block-level control signals
- Function arguments mapped into the
s_axiliteinterface
s_axilite interface by default. To change the default block
protocol, specify the interface pragma as
follows:#pragma HLS INTERFACE mode=ap_ctrl_hs port=returnap_ctrl, as seen in Interfaces for Vivado IP Flow. However, if you are using an s_axilite interface in your IP, you can also
assign the block control protocol to that interface using the following
INTERFACE pragmas, as an
example:#pragma HLS INTERFACE mode=s_axilite port=return bundle=BUS_A
#pragma HLS INTERFACE mode=ap_ctrl_hs port=return bundle=BUS_AIn the Control Register Map, Vitis HLS reserves addresses 0x00 through 0x0C for the
block-level protocol signals and interrupt controls, as shown below:
| Address | Description |
|---|---|
| 0x00 | Control signals |
| 0x04 | Global Interrupt Enable Register |
| 0x08 | IP Interrupt Enable Register (Read/Write) |
| 0x0c | IP Interrupt Status Register (Read/TOW) |
The Control signals (0X00) contains ap_start, ap_done, ap_ready, and ap_idle; and in the case of ap_ctrl_chain the block protocol also contains ap_continue. These are the block-level interface signals which are
accessed through the s_axilite
adapter.
To start the block operation theap_start bit in the Control register must be set to 1. The
HLS engine will then proceed and read any inputs grouped into the AXI4-Lite slave interface from the register in the
interface.
When the block completes the operation, theap_done,ap_idleandap_ready
registers will be set by the hardware output ports and the results for any
output ports grouped into the s_axilite
interface read from the appropriate register.
For function arguments, Vitis HLS automatically assigns the address for each
argument or port that is assigned to the s_axilite interface. The tool will assign each port an
offset starting from 0x10, the lower
addresses being reserved for control signals. The size, or range of
addresses assigned to a port is dependent on the argument data type and the
port protocol used.
Because the variables grouped into an AXI4-Lite interface are function arguments which do not have
a default value in the C code, none of the argument registers in the s_axilite interface can be assigned a
default value. The registers can be implemented with a reset using the
config_rtl command, but they cannot
be assigned any other default value.
The Control Register Map generated by Vitis HLS for the ap_ctrl_hs block control protocol is provided below:
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (COR/TOW)
// bit 1 - ap_ready (COR/TOW)
// others - reserved
// 0x10 : Data signal of a
// bit 7~0 - a[7:0] (Read/Write)
// others - reserved
// 0x14 : reserved
// 0x18 : Data signal of b
// bit 7~0 - b[7:0] (Read/Write)
// others - reserved
// : Control signal of b
// bit 0 - b_ap_vld (Read/Write/SC)
// others - reserved
// 0x20 : Data signal of c_i
// bit 7~0 - c_i[7:0] (Read/Write)
// others - reserved
// 0x24 : reserved
// 0x28 : Data signal of c_o
// bit 7~0 - c_o[7:0] (Read)
// others - reserved
// 0x2c : Control signal of c_o
// bit 0 - c_o_ap_vld (Read/COR)
// others - reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)