When the inner loop of a loop hierarchy is pipelined, Vitis HLS flattens the nested loops to reduce latency and improve overall throughput by removing any cycles caused by loop transitioning (the checks performed on the loop index when entering and exiting loops). Such checks can result in a clock delay when transitioning from one loop to the next (entry and/or exit).
Imperfect loop nests, or the inability to flatten them, results in additional
clock cycles to enter and exit the loops. When the design contains nested loops, analyze
the results to ensure as many nested loops as possible have been flattened: review the
log file or look in the synthesis report for cases, as shown in Loop Pipelining, where the loop labels have been merged (LOOP_I and LOOP_J are now
reported as LOOP_I_LOOP_J).