This lab application note describes combining isolation design flow (IDF) and dynamic function eXchange (DFX) within a single design. With the help of this application note, designers can develop a fail-safe single chip solution, using the Xilinx® device IDF combined with the Dynamic Function eXchange (DFX), which allows modification of an operating FPGA design, by loading a dynamic configuration file.
This application note follows the rules defined in Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) and the DFX rules defined in Vivado Design Suite User Guide: Dynamic Function eXchange (UG909). Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for details on the combined flow of IDF + DFX.
An IDF design example is provided in the Isolation Design Example for Zynq Ultrascale+ MPSoC Application Note (XAPP1336). For a DFX example on UltraScale+™ devices, refer to the Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947). The document is written with the assumption that the reader is familiar with both IDF and DFX methodologies.
Download the reference design files for this application note from the AMD-Xilinx website. For detailed information about the design files, see the Reference Design section.